[VHDL实例]三态总线(注2)

 

VHDL:Tri-State Buses

prebus.vhd 

LIBRARY IEEE;

    USE ieee.std_log_1164.ALL;

ENTITY prebus IS

    PORT(

        my_in  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

        sel    : IN STD_LOGIC;

        my_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END prebus;

ARCHITECTURE cpld OF prebus IS

BEGIN

    my_out <= "ZZZZZZZZ"

    WHEN (sel = '1')

    ELSE my_in;

END cpld;