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[VHDL实例]解复用器

 
------------------------------------------------------------------------------------
-- DESCRIPTION   :  Demultiplexer
--                  Width: 8
--                  Number of terminals: 4
--                  Output enable active: HIGH
--                  Output active : HIGH
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOG_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity dmux is
          port (
                    EN : in STD_LOGIC;
                    DATA_OUT0 : out STD_LOGIC_VECTOR (7 downto 0);
                    DATA_OUT1 : out STD_LOGIC_VECTOR (7 downto 0);
                    DATA_OUT2 : out STD_LOGIC_VECTOR (7 downto 0);
                    DATA_OUT3 : out STD_LOGIC_VECTOR (7 downto 0);
                    SEL : in STD_LOGIC_VECTOR (1 downto 0);
                    DATA_IN : in STD_LOGIC_VECTOR (7 downto 0)
          );
end entity;
architecture dmux_arch of dmux is
constant NON_ACTIVE : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
begin
 
          DATA_OUT0 <= DATA_IN when (SEL = 0) and (EN = '1') else NON_ACTIVE;
          DATA_OUT1 <= DATA_IN when (SEL = 1) and (EN = '1') else NON_ACTIVE;
          DATA_OUT2 <= DATA_IN when (SEL = 2) and (EN = '1') else NON_ACTIVE;
          DATA_OUT3 <= DATA_IN when (SEL = 3) and (EN = '1') else NON_ACTIVE;
 
end architecture;

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